The invention relates to a method to generate a magnitude result of a mathematic operation of two decimal operands within one cycle in a decimal arithmetic logic unit structure, particularly wherein the decimal operands are in hexadecimal sign magnitude format, plus a decimal arithmetic logic unit structure to perform such a method.
Mainframe computers can increase the speed of decimal operations. For example, two operands X, Y to be added with or to be subtracted from each other are in a sign magnitude hexadecimal format. In sign magnitude hexadecimal format each digit i of the operands X, Y and of the result of the mathematic operation is represented by a four-bit code with the values ‘0’ to ‘9’ encoded as ‘0000’ to ‘1001’. The hexadecimals ‘A’, ‘C’, ‘E’, ‘F’ indicate a positive algebraic sign, wherein ‘B’ and ‘D’ indicate a negative sign. Before an arithmetical operation takes place, the signs are removed from the operands, and it is decided whether an effective decimal addition or an effective decimal subtraction is being performed.
In case of an effective subtraction, the magnitude of the result can be less than zero, if the minuend X is smaller than the subtrahend Y. In this case, an additional cycle is necessary to re-complement the result into a sign magnitude format, as known in the art.
The general rule for binary decimal operations like additions (ADD) and subtractions (SUB) of two operands X, Y is as follows:ADD: S=X+Y+6digitwise 
Thereby, if the digit carry-out (DCyOuti) of a digit i of the result S is zero, i.e. DCyOuti=0, then the digit i has to be corrected by subtracting six. Otherwise, the digit i is correct.SUB: S=A−B 
Thereby, if DCyOuti=0, then the digit i is corrected by subtracting 6. Otherwise, digit i is correct. Further, if the carry-out (CyOut) of the most significant digit (MSD) on the left is zero, i.e. DCyOutMSD=CyOut=0, the result S is negative and must be re-complemented to get the magnitude M.
The procedure of a subtraction with negative result S is explained with reference to the following example.
Two decimal operands X=2856 and Y=5947 are subtracted from each other. The decimal result S has the magnitude M 3091 and is negative.
The digits 2856 of the operand X in hexadecimal are represented by the four-bit codes a, b, c, d
dcBaX:0010100001010110
with the digit ‘a’ as the least significant digit (LSD) and the digit ‘d’ as the most significant digit (MSD).
The digits 5947 of the operand Y in hexadecimal are represented by the four-bit codes
dcBaY:0101100101000111
To perform the subtraction, the two's complement of the inverted operand Y′ is added with the first operand X. To do so, first the operand Y is inverted bitwise to
dcBaY′:1010011010111000
To get the two's complement of the operand Y, further a carry-in (CyIn) of one, i.e. CyIn=1, is added to the least significant digit (LSD) ‘a’ on the right of Y′. Considering this, the subtraction X−Y is performed according to
dcBaX:0010100001010110+ Y′:+1010011010111000+ CyIn:+1wherein the following DCyOuti are generated by the digitwise addition
dcBaDCyOuti:0010
The DCyOuti of the digits i are used as digit carry-in (DCyIni+1) for the next higher digits i+1 to the left according to:
dcBaX:0010100001010110+ Y′:+1010011010111000+ CyIn:+1+ DCyIni + 1:+0010=1100111100001111
Thereby, any DCyOuti=0 indicates a digitwise minus six correction for the particular digit according to
dcBaX:0010100001010110+ Y′:+1010011010111000+ CyIn:+1DCyIni + 1:+0010=1100111100001111DCyOuti:0010− 6:+101010101010iR:=0110100100001001decimal:6909with the intermediate result iR. The result of the operation includes an intermediate result iR since the DCyOuti of the digit ‘d’ on the left that is the MSD is zero. The DCyOuti of the digit ‘d’ is the CyOut. CyOut=0 indicates a recomplementation of the result of the operation performed to obtain the magnitude M of the result S of the subtraction.
To do so, a second cycle is performed, wherein the first operand X is zero and the second operand Y is the intermediate result iR:
dcBa 0000:0000000000000000− 6909:+1001011011110110CyIn:+1=1001011011110111DCyOuti:0000  − 6:+1010101010101010M:=0011000010010001decimal:3091
To perform such operations within a microprocessor, a decimal arithmetic logic unit structure (ALU) ALU1 as shown in FIG. 1 is used. FIG. 1 shows an embodiment of a carry select structure which known in the art. However, the sum can be achieved with any other adder structure which achieves the performance requirements.
Two decimal operands X, Y, minuend X and subtrahend Y, are provided by registers R1, R2. The register R1 is connected with a first input of a digit carry network DCN and with first inputs of two pre-sum logics P1, P2. The output of the register R2 is connected to the input of an inverter I and with an adder A1 in parallel to the inverter I. The inverter performs a bitwise inversion of the operand Y. The adder A1 performs a digitwise +6 addition of the operand Y that is needed for effective decimal additions.
The output of the inverter I is connected to a first input of a first multiplexer M1. The output of the adder A1 is connected to a second input of the first multiplexer M1. A signal EDA indicating an effective decimal addition is used to select the second input of the multiplexer M1 as an output. The orthogonal signal of EDA, indicating an effective decimal subtraction is used to select the first input of the multiplexer M1 as an output. The signal EDA is generated by an operation decoder (not shown). The signal EDA and its mutual exclusive signal EDS (effective decimal subtraction), can be generated by inverting the other. The output of the multiplexer M1 is connected to a second input of the digit carry network DCN and to the second inputs of the two pre-sum logics P1, P2.
The digit carry network DCN operates according to conventional carry look ahead techniques by using generate and propagate functions of the operand bits to generate the CyOut of the MSD. Furthermore, the digit carry network DCN generates DCyOuti, i.e. DCyIni+1, for each of the decimal digit positions. The digit carry network DCN further has a third input. The signal EDA is inverted and fed to said third input. The inverted signal EDA indicates CyIn=1 for the LSD which is needed to generate the two's complement of the subtrahend Y for performing subtractions.
The pre-sum logics P1, P2 have third inputs each, wherein the third input of the pre-sum logic P1 is fed with an input of ‘0’ and the third input of the pre-sum logic P2 is fed with an input of ‘1’. Depending on the operand version received, the pre-sum logic P1 generates from the operands digitwise preliminary results X+Y+6 or X−Y on the assumption that DCyIni+1=0 and the pre-sum logic P2 generates from the operands digitwise preliminary results X+Y+6 or X−Y on the assumption that DCyIni+1=1.
The pre-sum selection is performed by a second multiplexer M2 which selects one of the pre sums X+Y+6 and X−Y digitwise, depending on DCyIni+1 provided by the digit carry network DCN into the digit position shown.
The structure of FIG. 1 is also known as Carry Select Adder Structure. It can be of any type, e.g. a Carry Propagation Structure CPA. As known in the art, only the digitwise +6 and −6 feature is required, but the carry network and the preliminary sum can be generated with any appropriate known structure.
The following describes a configuration having only the path of one digit. The complete width of the result is formed of several digits, e.g. 8 digits. The output of the second multiplexer M2 is split into two parallel paths. The first path is directly connected to a first input of a third multiplexer M3. The second path leads to a second adder A2 that performs a digitwise −6 correction. The result of that digitwise −6 correction is fed to a second input of the third multiplexer. Depending on the appropriate DigitCyOut of the digit carry network DCN, one of the two inputs of the third multiplexer M3 is selected as an output. If DigitCyOut=1, the second input is selected, i.e. no correction needed. If DigitCyOut=0, the first input is selected, i.e. the digit has to be corrected by subtracting 6. If the CyOut of the MSD is 1, the output of all digits of the third multiplexer M3 is the magnitude M of the complete result. If the CyOut of the MSD is 0, the output of the third multiplexer M3 is the intermediate result iR that has to be recomplemented in order to get the magnitude M of the result S. To recomplement the intermediate result iR a second cycle has to be performed within the same hardware structure, with X=0 and Y=iR.
FIG. 3 shows another conventional decimal arithmetic logic unit structure ALU2 which, compared to the decimal arithmetic logic unit structure of FIG. 1, is enhanced to additionally perform binary mathematic operations. Thereby the same reference numerals are used as in FIG. 1. The enhancement is achieved by a substitution of the inverter I in FIG. 1 by a XOR-gate XO. Furthermore logic within the Block CDDC in FIG. 3 controls the switching levels of the multiplexer M3. For binary operation always the second level of this multiplexer M3 is active. In case of an effective decimal addition the operand Y provided by the register R2 runs via the adder A1. In case of an effective subtraction, binary as well as decimal, the operand Y runs via the XOR-gate XO in order to be inverted. This is controlled by a general subtraction signal any_Sub AS. This signal any_Sub AS can also be used as CarryIn for the DCN in order to achieve the two's complement within the DCN. If a binary operation is performed, no correction occurs at the third multiplexer M3.
Improvements to the structure of FIG. 1 are known, for example, as described in U.S. Pat. No. 5,944,772 and US 2006/0031279 A1. However, such improvements are directed to the reduction of the path delay. All known structures require an additional cycle in case of negative results to obtain the magnitude.